Describe enhancement-mode NMOS operation and how gate voltage controls channel conduction.

• A. Enhancement-mode NMOS: channel exists at zero gate voltage; applying V_GS above threshold turns it off.
• B. Enhancement-mode NMOS: channel exists at zero gate voltage; increasing V_GS increases conduction.
• C. Enhancement-mode NMOS: no channel at zero gate voltage; applying V_GS above threshold creates channel; current flows when V_DS applied.
• D. Enhancement-mode NMOS: conduction is independent of gate voltage; channel always present.

Answer: (C)

In an enhancement-mode NMOS, there is no conductive channel when the gate voltage is zero. The gate, separated from the silicon by an insulating oxide, creates an electric field that can invert the surface when V_GS exceeds a threshold. Once V_GS is above this threshold, an n-type inversion channel forms between the source and drain, allowing current to flow when a drain-source voltage is applied. The gate voltage then controls how conductive that channel is: increasing V_GS (above threshold) increases the electron density in the channel, lowering its resistance and increasing the drain current for a given V_DS. If V_GS is below threshold, the channel is not present and current remains essentially off until a channel is created by applying a sufficient gate voltage.

That’s why the correct description is that no channel exists at zero gate voltage; applying V_GS above threshold creates the channel, and current flows when V_DS is applied. The other statements imply a channel at zero gate voltage or conduction independent of gate voltage, which does not match enhancement-mode NMOS behavior.